1. Technical Field
The present invention relates to automated digital logic synthesis and more specifically it is directed to an improved integrated circuit design method for performing concurrent buffer insertion and layer assignment within an integrated circuit design to achieve optimal timing while maintaining speed and efficient use of resources.
2. Description of the Related Art
The present invention has particular application in the computer aided design of integrated circuits utilizing nanometer technology where increased resistivity due to finer metal layer widths and longer interconnect delays are a concern. Buffer or repeater insertion is a popular technique to reduce such interconnect delay. The number of block-level nets requiring buffer insertion rises as process technology scales down and a larger number of buffers are required to meet interconnect timing requirements for specific circuit designs. These additional buffers occupy a lot of active silicon and routing area and a rapid increase in the number of buffers can yield designs which are not feasible. The reduction in metal layer width increases the resistance of the interconnect wires which may be compensated for utilizing vertical scaling and additional metal layers. For example, in 65 nm technologies, there may be three metal layer horizontal/vertical pairs available for logic and physical synthesis. The upper metal layers are less resistive as a result of increased geometries and inter-buffer separation may be much larger, reducing the need for additional buffers.
As a result, techniques for metal layer assignment and buffering are increasingly important for optimal wire and buffer synthesis which can meet electrical and timing constraints of a VLSI silicon design. These techniques are utilized several times during the design process and consequently, the use of a fast reliable algorithm is critical.